| tech,0-2-P99-1058,ak | To verify <term> hardware designs </term> by <term> model checking </term> , <term> circuit specifications </term> are commonly expressed in the <term> temporal logic CTL </term> . <term> Automatic conversion </term> of <term> English </term> to <term> CTL </term> requires the definition of an appropriately <term> restricted subset </term> of <term> English </term> . | #30946 To verify hardware designs by model checking, circuit specifications are commonly expressed in the temporal logic CTL. Automatic conversion of English to CTL requires the definition of an appropriately restricted subset of English. |
