| other,5-1-P99-1058,ak | verify <term> hardware designs </term> by <term> | model checking | </term> , <term> circuit specifications </term> | #30932 To verify hardware designs bymodel checking, circuit specifications are commonly expressed in the temporal logic CTL. | |
| other,15-1-P99-1058,ak | </term> are commonly expressed in the <term> | temporal logic CTL | </term> . <term> Automatic conversion </term> | #30942 To verify hardware designs by model checking, circuit specifications are commonly expressed in thetemporal logic CTL. | |
| other,17-3-P99-1058,ak | exploited to derive a hierarchy of <term> | subsets | </term> . Our strategy avoids potential difficulties | #30980 We show how the limited semantic expressibility of CTL can be exploited to derive a hierarchy ofsubsets. | |
| other,34-4-P99-1058,ak | in the <term> subset </term> possess a <term> | CTL translation | </term> . This paper presents a new method | #31016 Our strategy avoids potential difficulties with approaches that take existing computational semantic analyses of English as their starting point--such as the need to ensure that all sentences in the subset possess aCTL translation. | |
| other,15-2-P99-1058,ak | appropriately <term> restricted subset </term> of <term> | English | </term> . We show how the limited <term> semantic | #30961 Automatic conversion of English to CTL requires the definition of an appropriately restricted subset ofEnglish. | |
| other,8-1-P99-1058,ak | </term> by <term> model checking </term> , <term> | circuit specifications | </term> are commonly expressed in the <term> | #30935 To verify hardware designs by model checking,circuit specifications are commonly expressed in the temporal logic CTL. | |
| other,14-4-P99-1058,ak | computational semantic analyses </term> of <term> | English | </term> as their starting point -- such as | #30996 Our strategy avoids potential difficulties with approaches that take existing computational semantic analyses ofEnglish as their starting point--such as the need to ensure that all sentences in the subset possess a CTL translation. | |
| other,2-1-P99-1058,ak | been shown to be NP-hard . To verify <term> | hardware designs | </term> by <term> model checking </term> , <term> | #30929 To verifyhardware designs by model checking, circuit specifications are commonly expressed in the temporal logic CTL. | |
| other,8-3-P99-1058,ak | <term> semantic expressibility </term> of <term> | CTL | </term> can be exploited to derive a hierarchy | #30971 We show how the limited semantic expressibility ofCTL can be exploited to derive a hierarchy of subsets. | |
| other,28-4-P99-1058,ak | such as the need to ensure that all <term> | sentences | </term> in the <term> subset </term> possess | #31010 Our strategy avoids potential difficulties with approaches that take existing computational semantic analyses of English as their starting point--such as the need to ensure that allsentences in the subset possess a CTL translation. | |
| other,5-3-P99-1058,ak | English </term> . We show how the limited <term> | semantic expressibility | </term> of <term> CTL </term> can be exploited | #30968 We show how the limitedsemantic expressibility of CTL can be exploited to derive a hierarchy of subsets. | |
| other,12-2-P99-1058,ak | the definition of an appropriately <term> | restricted subset | </term> of <term> English </term> . We show how | #30958 Automatic conversion of English to CTL requires the definition of an appropriatelyrestricted subset of English. | |
| tech,10-4-P99-1058,ak | with approaches that take existing <term> | computational semantic analyses | </term> of <term> English </term> as their starting | #30992 Our strategy avoids potential difficulties with approaches that take existingcomputational semantic analyses of English as their starting point--such as the need to ensure that all sentences in the subset possess a CTL translation. | |
| tech,0-2-P99-1058,ak | the <term> temporal logic CTL </term> . <term> | Automatic conversion | </term> of <term> English </term> to <term> CTL | #30946 To verify hardware designs by model checking, circuit specifications are commonly expressed in the temporal logic CTL.Automatic conversion of English to CTL requires the definition of an appropriately restricted subset of English. | |
| other,31-4-P99-1058,ak | that all <term> sentences </term> in the <term> | subset | </term> possess a <term> CTL translation </term> | #31013 Our strategy avoids potential difficulties with approaches that take existing computational semantic analyses of English as their starting point--such as the need to ensure that all sentences in thesubset possess a CTL translation. | |
| other,5-2-P99-1058,ak | conversion </term> of <term> English </term> to <term> | CTL | </term> requires the definition of an appropriately | #30951 Automatic conversion of English toCTL requires the definition of an appropriately restricted subset of English. | |
| other,3-2-P99-1058,ak | <term> Automatic conversion </term> of <term> | English | </term> to <term> CTL </term> requires the definition | #30949 Automatic conversion ofEnglish to CTL requires the definition of an appropriately restricted subset of English. |
