<term>
Automatic conversion
</term>
of
<term>
English
</term>
to
<term>
CTL
</term>
requires the definition of an appropriately
<term>
restricted subset
</term>
of
<term>
English
</term>
.
#30958Automatic conversion of English to CTL requires the definition of an appropriatelyrestricted subset of English.
other,14-4-P99-1058,ak
Our strategy avoids potential difficulties with approaches that take existing
<term>
computational semantic analyses
</term>
of
<term>
English
</term>
as their starting point -- such as the need to ensure that all
<term>
sentences
</term>
in the
<term>
subset
</term>
possess a
<term>
CTL translation
</term>
.
#30996Our strategy avoids potential difficulties with approaches that take existing computational semantic analyses ofEnglish as their starting point--such as the need to ensure that all sentences in the subset possess a CTL translation.
other,15-1-P99-1058,ak
To verify
<term>
hardware designs
</term>
by
<term>
model checking
</term>
,
<term>
circuit specifications
</term>
are commonly expressed in the
<term>
temporal logic CTL
</term>
.
#30942To verify hardware designs by model checking, circuit specifications are commonly expressed in thetemporal logic CTL.
other,15-2-P99-1058,ak
<term>
Automatic conversion
</term>
of
<term>
English
</term>
to
<term>
CTL
</term>
requires the definition of an appropriately
<term>
restricted subset
</term>
of
<term>
English
</term>
.
#30961Automatic conversion of English to CTL requires the definition of an appropriately restricted subset ofEnglish.
other,17-3-P99-1058,ak
We show how the limited
<term>
semantic expressibility
</term>
of
<term>
CTL
</term>
can be exploited to derive a hierarchy of
<term>
subsets
</term>
.
#30980We show how the limited semantic expressibility of CTL can be exploited to derive a hierarchy ofsubsets.
other,2-1-P99-1058,ak
To verify
<term>
hardware designs
</term>
by
<term>
model checking
</term>
,
<term>
circuit specifications
</term>
are commonly expressed in the
<term>
temporal logic CTL
</term>
.
#30929To verifyhardware designs by model checking, circuit specifications are commonly expressed in the temporal logic CTL.
other,28-4-P99-1058,ak
Our strategy avoids potential difficulties with approaches that take existing
<term>
computational semantic analyses
</term>
of
<term>
English
</term>
as their starting point -- such as the need to ensure that all
<term>
sentences
</term>
in the
<term>
subset
</term>
possess a
<term>
CTL translation
</term>
.
#31010Our strategy avoids potential difficulties with approaches that take existing computational semantic analyses of English as their starting point--such as the need to ensure that allsentences in the subset possess a CTL translation.
other,3-2-P99-1058,ak
<term>
Automatic conversion
</term>
of
<term>
English
</term>
to
<term>
CTL
</term>
requires the definition of an appropriately
<term>
restricted subset
</term>
of
<term>
English
</term>
.
#30949Automatic conversion ofEnglish to CTL requires the definition of an appropriately restricted subset of English.
other,31-4-P99-1058,ak
Our strategy avoids potential difficulties with approaches that take existing
<term>
computational semantic analyses
</term>
of
<term>
English
</term>
as their starting point -- such as the need to ensure that all
<term>
sentences
</term>
in the
<term>
subset
</term>
possess a
<term>
CTL translation
</term>
.
#31013Our strategy avoids potential difficulties with approaches that take existing computational semantic analyses of English as their starting point--such as the need to ensure that all sentences in thesubset possess a CTL translation.
other,34-4-P99-1058,ak
Our strategy avoids potential difficulties with approaches that take existing
<term>
computational semantic analyses
</term>
of
<term>
English
</term>
as their starting point -- such as the need to ensure that all
<term>
sentences
</term>
in the
<term>
subset
</term>
possess a
<term>
CTL translation
</term>
.
#31016Our strategy avoids potential difficulties with approaches that take existing computational semantic analyses of English as their starting point--such as the need to ensure that all sentences in the subset possess aCTL translation.
other,5-1-P99-1058,ak
To verify
<term>
hardware designs
</term>
by
<term>
model checking
</term>
,
<term>
circuit specifications
</term>
are commonly expressed in the
<term>
temporal logic CTL
</term>
.
#30932To verify hardware designs bymodel checking, circuit specifications are commonly expressed in the temporal logic CTL.
other,5-2-P99-1058,ak
<term>
Automatic conversion
</term>
of
<term>
English
</term>
to
<term>
CTL
</term>
requires the definition of an appropriately
<term>
restricted subset
</term>
of
<term>
English
</term>
.
#30951Automatic conversion of English toCTL requires the definition of an appropriately restricted subset of English.
other,5-3-P99-1058,ak
We show how the limited
<term>
semantic expressibility
</term>
of
<term>
CTL
</term>
can be exploited to derive a hierarchy of
<term>
subsets
</term>
.
#30968We show how the limitedsemantic expressibility of CTL can be exploited to derive a hierarchy of subsets.
other,8-1-P99-1058,ak
To verify
<term>
hardware designs
</term>
by
<term>
model checking
</term>
,
<term>
circuit specifications
</term>
are commonly expressed in the
<term>
temporal logic CTL
</term>
.
#30935To verify hardware designs by model checking,circuit specifications are commonly expressed in the temporal logic CTL.
other,8-3-P99-1058,ak
We show how the limited
<term>
semantic expressibility
</term>
of
<term>
CTL
</term>
can be exploited to derive a hierarchy of
<term>
subsets
</term>
.
#30971We show how the limited semantic expressibility ofCTL can be exploited to derive a hierarchy of subsets.
tech,0-2-P99-1058,ak
To verify
<term>
hardware designs
</term>
by
<term>
model checking
</term>
,
<term>
circuit specifications
</term>
are commonly expressed in the
<term>
temporal logic CTL
</term>
.
<term>
Automatic conversion
</term>
of
<term>
English
</term>
to
<term>
CTL
</term>
requires the definition of an appropriately
<term>
restricted subset
</term>
of
<term>
English
</term>
.
#30946To verify hardware designs by model checking, circuit specifications are commonly expressed in the temporal logic CTL.Automatic conversion of English to CTL requires the definition of an appropriately restricted subset of English.
tech,10-4-P99-1058,ak
Our strategy avoids potential difficulties with approaches that take existing
<term>
computational semantic analyses
</term>
of
<term>
English
</term>
as their starting point -- such as the need to ensure that all
<term>
sentences
</term>
in the
<term>
subset
</term>
possess a
<term>
CTL translation
</term>
.
#30992Our strategy avoids potential difficulties with approaches that take existingcomputational semantic analyses of English as their starting point--such as the need to ensure that all sentences in the subset possess a CTL translation.